1. Field of the Invention
The present invention relates to a non-overlapping two-phase signal generator. A non-overlapping two-phase signal is composed of two trains of pulses with the pulses of one train not overlapping with those of the other train in time.
2. Prior Art
Japanese Patent Application Laid-Open No. 4-20,016 discloses one example of a non-overlapping three-phase signal generator. Referring to FIG. 4(A), it comprises a loop-like series connection of three delay circuits to form a ring oscillator 140. Each delay circuit comprises a MOS variable resistance circuit having an inverter INV11, INV12 or INV13 on its input side and a capacitor C11, C12 or C13 on its output side. Specifically, one electrode of each capacitor is connected to the MOS variable resistance circuit, and the other electrode is grounded. Each MOS variable resistance circuit is adapted to be controlled by complementary control signals Vin and inverted Vin. This ring-like arrangement forms a positive feed-back circuit in which the pre-inversion and the CR time delay produced by the capacitor and MOS variable resistor at each stage cause push-pull operations around the ring.
In this example, all circuit elements have the same characteristics: inverters INV11, INV12 and INV13 have the same logic threshold; capacitors C11, C12 and C13 have the same capacitance; and MOS variable resistances S11, S12 and S13 have the same characteristics. Three trains of pulses P1, P2 and P3 appear at the output terminals of the delay circuits. Due to the same characteristics of all circuit elements the waveform of each pulse train has the same duty and the same pulse-to-pulse duration as those of the other trains, as seen from FIG. 4(B).
The logic circuit 124 is responsive to these clock signals P1, P2 and P3 for producing non-overlapping three-phase clock pulses. It is composed of three AND gates 11, 12 and 13, which function according to the following logic equations: EQU CP1=P1.multidot.P2; EQU CP2=P1.multidot.P3; and EQU CP3=P2.multidot.P3.
The clock pulses thus produced are shown in FIG. 4(B). As seen from FIG. 4(A), the output terminal of each delay stage is connected to AND gates selected in the logic circuit 124 via an associated buffer BUF11, BUF12 or BUF13.
Japanese Patent Application Laid-Open No. 5-100,768 discloses one example of a non-overlapping two-phase signal generator. Referring to FIG. 5(A), it comprises a reference clock signal generator 201 for generating reference clock signals at a frequency twice s high as clock signals, a first 1/2 frequency-divider 204 having a non-inversion circuit 202 associated therewith, a second 1/2 frequency-divider 205 having an inversion circuit 202 associated therewith, and a clock signal generator 206. Each 1/2 frequency-divider 204 or 205 is connected to the reference clock signal generator 201 to reduce the frequency of the reference clock signal to half, that is, the frequency of clock signals. The clock signal generator 206 is responsive to the signals from the 1/2 frequency dividers 204 and 205 for producing clock pulses in the form of non-overlapping two-phase signals. The duration or width of each clock pulse is composed of a variable section and a fixed section.
The clock signal generator 206 comprises: a first AND gate 63 of which one input terminal is connected to the first 1/2 frequency-divider 204 and of which the other input terminal is connected to the second 1/2 frequency-divider 205 via an associated inverter 62; a second AND gate 64 of which one input terminal is connected to the first 1/2 frequency-divider 204 via an associated inverter 61 and of which the other input terminal is connected to the second 1/2 frequency-divider 205; a first series of delay gates 65 connected to the output terminal of the AND gate 63; a second series of delay gates 66 connected to the output terminal of the AND gate 64; first OR gate 67, of which one input terminal is connected to the output terminal of the AND gate 63 and of which the other input terminal is connected to the output terminal of the first series of delay gates 65; and a second OR gate 68 of which one input terminal is connected to the output terminal of the AND gate 64 and of which the other input terminal is connected to the output terminal of the second series of delay gates 66. Clock pulses C1 and C2 appear at the output terminals of the first and second OR gates 67 and 68.
The AND gate 63 and 64 function to form the fixed section of clock pulse, of which the duration is equal to the reference pulse duration. On the other hand, the series of delay gates 65 and 66 function to form the variable section of clock pulse. The delays of gates 65 and 66 are determined during design stage. The delay of gates 65 and 66 vary because of the fluctuations of the voltage of power supply and temperature of gates and deviation of each gate. The OR gate 67 or 68 functions to form clock pulses C1 or C2 as an integration of these fixed and variable sections.
The number of delay gates is determined to provide a required amount of time delay in consideration of the delay amount in each gate, clock cycles and other designing factors.
With reference to FIG. 5(B), the operation of the circuit is described as follow. The signal names in FIG. (B) corresponds to those in FIG. 5(A).
First, the reference clock pulses C are generated by the oscillator 201 to be directed to both of the non-inversion circuit 202 and the inversion circuit 203. The non-inversion circuit 202 produces a time delay of the input signal as long as that produced by the inversion circuit 203. The non-inverted and inverted signals are directed to the 1/2 frequency-dividers 204 and 205 respectively, thus allowing the pulse signals Q1 and Q2 whose periods are twice as long as the reference clock signal C to appear at their output terminals. The pulse signal Q2 lags by the duration of reference pulse C behind the pulse signal Q1.
These pulse signals Q1 and Q2 are directed to the clock signal generator 206. Specifically, the pulse signal Q1 is directed to one input terminal of the AND gate 63, and at the same time to one input terminal of the AND gate 64 via the inverter 61. Likewise, the pulse signal Q2 is directed to the other input terminal of the AND gate 63 via the inverter 62, and at the same time to the other input terminal of the AND gate 64.
Then, the pulse signal R1 appears at the output terminal of the AND gate 63 to be directed to one terminal of the OR gate 67, and at the same time to the series of delay gates 65, thus causing the delayed pulse signal D1 to appear at the output terminal of the series of delay gates 65, and the delayed pulse signal D1 is applied to the other terminal of the OR gate 67. Finally the OR gate 67 produces clock signal C1 at its output terminal.
On the other hand, the pulse signal R2 appears at the output terminal of the AND gate 64 to be directed to one terminal of the OR gate 68, and at the same time to the series of delay gates 66, thus causing the delayed pulse signal D2 to appear at the output terminal of the series of delay gates 66, and the delayed pulse signal D2 is applied to the other terminal of the OR gate 68. Finally the OR gate 68 produces clock signal C2 at its output terminal.
As may be understood from the above, the reference clock signal C has a frequency twice as high as the clock signal C1 or C2, and the clock signal C2 lags by one cycle of the reference clock signal C behind the clock signal C1.
The circuit arrangement of FIG. 4 can provide non-overlapping three-phase signal CP1, CP2 and CP3, and can be modified to provide non-overlapping two-phase signal by selecting two signals among these three signals CP1, CP2 and CP3. The so selected signals, however, cannot have the same non-overlapping period. Also, there is an disadvantage that the delay time is determined by the product of resistance and capacitance, and therefore, the rises of the waveforms are not so sharp as to prevent appearance of whiskers on the clock pulse.
The circuit arrangement of FIG. 5 is complicated in structure, using so many circuit elements that it cannot work quickly. The resultant pulse width is determined as an integration of the reference clock pulse duration plus the delay amount provided by the delay circuit, and therefore, the settings of oscillation period, pulse duration, and non-overlapping period are difficult.